FPGA-Based Instrumentation Withstands the Chill of Deep Space
B&A Engineering princple engineer Ali Bakhish research was in the Xcell journal for Xilinx in the Aerospace & Defense section on page 24 of the journal. He gave detailed facts and illusrations on FPGA-based insrumentation to withstand the chill of deep space. Mr. Bakhish’s article was to demonstate how the Xilinx Virtex-5 is able to endure, operate and survive cryogenic temperatures and how NASA is onboard to use the components for their systems.
To read more about the article click on the link:
Xcell Journal Xilinx.pdf
Third Quarter 2012Xcell Journal 25Current and future NASA robotic-flight missions to outer planets and asteroids require avionics systems, computers,controllers and data-processing units capable of enduring the extreme low-temperature environments of deep space and lunar and Martian surfaces.With recent technological advances in FPGAs, it has become possible toarchitect a complete system-on-a-chip (SoC) using a single FPGA. Large FPGAs that are radiation-hardened by design (RHBD) have increased the number of gates per square inch,reduced power consumption per gate and included microprocessors, soft and hard IP, arithmetic modules, sizable onboard memory and analog-to-digital converters.
B&A Engineering (BAENG) conduct-ed studies with the Xilinx® Virtex®-5mixed-signal RHBD FPGA to address NASA’s need for protected, reliable data-acquisition controllers and computer electronics able to operate in cryogenic temperatures. This RHBD FPGA will be the workhorse of future NASA computer and data-handling systems targeted for outer-planet landing,orbiting and sample-retrieval missions. To conduct the experiment, BAENG designed and built a test board based on a commercial Xilinx XC5VLX30FPGA and support circuitry (resistors,capacitors and oscillator), as shown in Figure 1. What’s remarkable is that we found that the chip works at temperatures well below spec for a commercial part and even well below spec for a space-grade Xilinx FPGA.The FPGA included circuits using internal phase-locked loops (PLLs), as well as a ring oscillator and a number of basic circuits built from LUTs.During the test, we monitored both circuit functionality and FPGA power consumption. We disabled all the regulators,switches, resets and configuration-mode pins on the board with the exception of the 100-MHz oscillator.We simulated FPGA and externalflash memory voltages and currents,switches, resets and configuration-mode pins and monitored the musing external test equipment and power supplies.
For more read: Xcell Journal Xilinx.pdf